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Russ College of Engineering and Technology
Stocker Center
Athens, OH 45701

Avinash Karanth

Avinash Karanth
Director, Electrical Engineering and Computer Science Joseph K. Jachinowski Professor
Stocker Center 330
Center for Scientific Computing and Immersive Technologies
Electrical Engineering and Computer Science
karanth@ohio.edu
740.597.1481
https://oucsace.cs.ohio.edu/~avinashk/

Avinash Karanth received his PhD and MS from The University of Arizona in August 2006 and May 2003 respectively. Presently, he is the Chair of the School of Electrical Engineering and Computer Science (EECS) at Ohio University. He is also Joseph K. Jachinowski Professor in the School of EECS where he leads the Technologies for Emerging Computer Architecture Laboratory (TEAL) at Ohio University. His research interests include Computer Architecture, Machine Learning, Hardware Accelerators, Network-on-Chips (NoCs), Emerging Technologies (nanophotonics, wireless), Hardware Security, and Exascale Networks.    

Avinash Karanth has received the prestigious NSF CAREER Award in 2011, Presidential Research Scholar Award in 2017, Best Paper Award at the ICCD 2013 conference and his papers have been nominated for Best Paper at IEEE Design and Test in Europe (DATE) in 2019, IEEE Symposium on Network-on-Chips (NoCs) in May 2010 and IEEE Asia & South Pacific Design Automation Conference (ASP-DAC) in January 2009. His research has been sponsored by National Science Foundation (NSF), Air Force Research Lab (AFRL), Ohio Department of Higher Education (ODHE) and Advanced Micro Devices (AMD) grants. Further, he has published 100+ articles in peer-reviewed IEEE and ACM journals and conferences.    

He is an Associate Editor for IEEE Transactions on Computers and IEEE Transactions on Cloud Computing and he has been a co-Guest Editor for IEEE Transactions on Emerging Topics for Computing ('15-'16) and Journal of Parallel and Distributed (JPDC) ('10-'11). He was the co-Chair of the architecture track at IPDPS-2020 and vice-Chair of the EDA track at DAC-2021 and DAC-2022 conferences. He has served on the Program Committee of HPCA (2019), DAC (2018-19), NoCs (2016-19), MPSoC (2014-2019) ACM Nanocom (2016), Hot Interconnects ('10,’16,'17,'19) and external Program Committee for MICRO'12. He has served on multiple NSF panels and several departmental committees. He is the Senior Member of IEEE. 

Research Interests: computer architecture, parallel processing, chip multiprocessors (CMPs), network-on-chips (NoCs)

All Degrees Earned: Ph.D., Electrical and Computer Engineering, University of Arizona, 2006; M.S., Electrical and Computer Engineering, University of Arizona, 2003; B.E., Electronics and Communications, Manipal Institute of Technology, Mangalore University, 2000

Publications:

  • Randy Morris, Avinash Kodi and Ahmed Louri, “Reconfiguration of 3D Photonic On-chip Interconnects for Maximizing Performance and Improving Fault Tolerance,” 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-45), Vancouver, BC, Canada, Dec 1-5, 2012.
  • Randy Morris and Avinash Kodi, “Exploring the Design of 64 & 256-core Power-Efficient Nanophotonic Interconnects,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 16, no. 5, pp. 1386-1393, September/October 2010.
  • Dominic DiTomaso, Avinash Kodi, Savas Kaya and David Matolak, “iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture”, 19th Annual IEEE Symposium on High-Performance Interconnects (Hot Interconnects), Santa Clara, California, August 24-25, 2011.
  • Avinash Kodi, Ashwini Sarathy, and Ahmed Louri, “iDEAL: Inter-router Dual-function Energy- and Area-Efficient Link design for Network-on-Chip (NoC) Architecture,” Proceedings of the 35th International Symposium on Computer Architecture (ISCA-35), pp. 241-250, Beijing, China, June 21-25, 2008.
  • Avinash Kodi and Ahmed Louri, “Performance Adaptive Power-Aware Reconfigurable Optical Interconnects for HPC Systems,” Proceedings on ACM/IEEE Conference on High-Performance Networking and Computing, SuperComputing (SC’07), Reno, Nevada, November 10-16, 2007.

Awards:

  • NSF CAREER (2011-2016)

Journal Article, Academic Journal (50)

  • Li, Y., Louri, A., Karanth , A. (2024). A High-Performance and Energy-Efficient Photonic Architecture for Multi-DNN Acceleration. IEEE Transactions on Parallel and Distributed Systems; 35: 46-58.
  • Yue, Y., Baltes, M., Abuhajar, N., Sun, T., Karanth , A., Smith, C., Bihl, T., Liu, J. (2023). Spiking neural networks fine-tuning for brain image segmentation. 2023. Frontiers on Neuroscience; 17: https://www.frontiersin.org/articles/10.3389/fnins.2023.1267639/full.
  • Li, Y., Louri, A., Karanth , A. (2022). SPRINT: A High-Performance, Energy-Efficient, and Scalable Chiplet-based Accelerator with Photonic Interconnects for CNN Inference. 2. IEEE Transactions on Parallel and Distributed Systems (TPDS); 33: 2332-2345.
  • Li, Y., Louri, A., Karanth , A. (2022). ASCEND: A Scalable and Energy-Efficient Deep Neural Network Accelerator with Photonic Interconnects. 7. IEEE Transactions on Circuits and Systems - I; 69: 2730-2741.
  • Liu, S., Canan, T., Chenji, H., Laha, S., Kaya, S., Karanth , A. (2022). Exploiting Wireless Technology for Energy-Efficient Accelerators With Multiple Dataflows and Precision. 7. Picataway, NJ: EEE Transactions on Circuits and Systems I: Regular Papers; 69: 2742-2755. https://ieeexplore.ieee.org/abstract/document/9761387.
  • Bhamidipati, P., Karanth , A. (2022). HREN: A Hybrid Reliable and Energy-Efficient Network-on-Chip Architecture. 2. IEEE Transactions on Emerging Topics in Computing (TETC); 10: 537-548.
  • Canan, T., Kaya, S., Karanth , A., Chenji, H. (2021). Fine-Grain Reconfigurable Logic Circuits for Adaptive and Secure Computing via Work-Function Engineered Schottky Barrier FinFETs. 2. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC); 7: 150-158.
  • Fettes, Q., Karanth , A., Bunescu, R., Louri, A., Shiflett, K. (2020). Hardware-Level Thread Migration to Reduce On-Chip Data Movement via Reinforcement Learning. 11. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; 39: 3638-3649.
  • Qian, X., Wang, Y., Karanth , A. (2020). Guest Editors' Introduction to the Special Issue on Machine Learning Architectures and Accelerators. 7. IEEE Transactions on Computers; 69: 929-930.
  • Louri, A., Collet, J., Karanth , A. (2019). Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs. 1. ACM Journal on Emerging Technologies in Computing Systems (JETC); 15: http://329 Stocker Center, Electrical Engineering and Com.
  • Canan, T., Kaya, S., Karanth , A., Xin, H., Louri, A. (2019). Ambipolar SB-FinFETs: A New Path to Ultra-Compact Sub-10 nm Logic Circuits. 1. Piscataway, NJ: IEEE Transactions on Electron Devices; 66: 255 - 263. https://ieeexplore.ieee.org/document/8516397.
  • Fettes, Q., Clark, M., Bunescu, R., Karanth , A., Louri, A. (2018). Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques. IEEE Transactions on Computers; http://ace.cs.ohio.edu/~razvan/papers/draft-tc18.pdf.
  • Sefton, S., Siddiqui, T., St. Amour, N., Stewart, G., Karanth , A. (2018). GARUDA: Designing Energy-Efficient Hardware Monitors From High-Level Policies for Secure Information Flow. 11. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; 37: 2509-2518.
  • Karanth , A., Kaya, S., Sikder, A., Louri, A., Laha, S., Carbaugh, D., Xin, H., Wu, J., DiTomaso, D. (2018). Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies. IEEE Transactions on Sustainable Computing; http://10.1109/TSUSC.2018.2861362.
  • Vanwinkle, S., Karanth , A. (2018). SHARP: Shared Heterogeneous Architecture with Reconfigurable Photonic Network-on-Chip. 2. New York, NY, USA: J. Emerg. Technol. Comput. Syst.; 14: 25:1--25:22. http://doi.acm.org/10.1145/3185383.
  • Boraten, T., Karanth , A. (2018). Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC) Architectures. 3. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; 37: 682-695.
  • Boraten, T., Karanth , A. (2018). Mitigation of Hardware Trojan Based Denial-of-Service Attack for Secure NoCs. C. Orlando, FL, USA: J. Parallel Distrib. Comput.; 111: 24--38. https://doi.org/10.1016/j.jpdc.2017.06.014.
  • Rayess, W., Matolak, D., Kaya, S., Karanth , A. (2017). Antennas and channel characteristics for wireless networks on chips. 4. Wireless Personal Communications; 95: 5039--5056.
  • Wu, J., Karanth , A., Kaya, S., Louri, A., Xin, H. (2017). Monopoles Loaded With 3-D-Printed Dielectrics for Future Wireless Intrachip Communications. 12. IEEE Transactions on Antennas and Propagation; 65: 6838--6846.
  • Kennedy, M., Karanth , A. (2017). Laser Pooling: Static and Dynamic Laser Power Allocation for On-Chip Optical Interconnects. 15. IEEE/OSA Journal of Lightwave Technology; 35: 3159-3167.
  • Kennedy, M., Karanth , A. (2017). CLAP-NET: Bandwidth Adaptive and Power Regulated Optical Crossbar Architecture. Journal of Parallel and Distributed Computing (JPDC); 100: 130-139.
  • Kennedy, M., Karanth , A. (2016). CLAP-NET: Bandwidth adaptive optical crossbar architecture. Journal of Parallel and Distributed Computing.
  • DiTomaso, D., Karanth , A., Louri, A., Bunescu, R. (2015). Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures. 12. IEEE Transactions on Computers; 64: 3555-3568. http://doi.ieeecomputersociety.org/10.1109/TC.2015.2401013.
  • DiTomaso, D., Karanth , A., Matolak, D., Kaya, S., Laha, S., Rayess, W. (2015). A-WiNoC: Adaptive Wireless Network-on-Chip Architecture Using Energy-Efficient Transceivers. 12. IEEE: Trans. on Parallel and Distributed Systems; 26: 3289-3302. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6991560&isnumber=7323921.
  • Laha, S., Kaya, S., Matolak, D., Rayess, W., DiTomaso, D., Karanth , A. (2015). A New Frontier in Ultra-low Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects. 2. IEEE: IEEE Transactions on Computer Aided Design for Integrated Circuits and Systems; 34: 186-198. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6982195&isnumber=7012128.
  • Karanth , A., Neel, B., Brantley, W. (2014). Photonic Interconnects for Exascale and Datacenter Architectures. 5. IEEE Micro Magazine; 34: 18-30. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6866037.
  • Laha, S., Kaya, S., Karanth , A., Matolak, D. (2014). A 60 GHz High Gain InGaAs pHEMT Power Amplifier with Microstrip Transmission Lines. Analog Integrated Circuits and Signal Processing.
  • Morris, R., Karanth , A., Louri, A., Whaley, R. (2014). 3D Stacked Nanophotonic Architecture with Minimal Reconfiguration. 1. IEEE Transactions on Computers; 63: 243-255. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6256662.
  • Morris, R., Jolley, E., Karanth , A. (2014). Extending the Performance and Energy-Efficiency of Nanophotonic Interconnects for Shared Memory Multicores . 1. IEEE Transactions on Parallel and Distributed Systems; 25: 83-92. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6463390.
  • Sun, J., Lysecky, R., Shankar, K., Karanth , A., Louri, A., Wang, j. (2014). Workload Assignment Considering NBTI Degradation in Multi-core Systems. 1. ACM Journal on Emerging Technologies in Computing Systems; 10: 1-22. http://dl.acm.org/citation.cfm?id=2539124.
  • DiTomaso, D., Morris, R., Karanth , A., Sarathy, A., Louri, A. (2013). Extending the Energy-Efficiency and Performance with Channel Buffers, Crossbars and Topology Analysis for NoCs. 11. IEEE Transactions on VLSI; 21: 2141-2154.
  • Matolak, D., Kaya, S., Karanth , A. (2013). Channel Modeling for Wireless Networks-on-Chips . 6. IEEE Wireless Communications Magazine; 51: 180-186.
  • Matolak, D., Karanth , A., Kaya, S., DiTomaso, D., Laha, S., Rayess, W. (2012). Wireless Networks-on-Chips: Architecture, Wireless Channel, and Devices. 5. IEEE Wireless Communications Magazine; 19: 58-65. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6339473.
  • Neel, B., Morris, R., DiTomaso, D., Karanth , A. (2012). SPRINT: Scalable Photonic Switching Fabric for High-Performance Computing (HPC). 9. IEEE/OSA Journal of Optical Communications and Networking (JOCN); 4: A37-A48.
  • Morris, R., Karanth , A. (2010). Exploring the Design of 64 & 256-core Power Efficient Nanophotonic Interconnect. 5. 16: 1386-1393.
  • Karanth , A., Louri, A. (2009). Multi-Dimension and Reconfigurable Optical Interconnects for High-Performance Computing(HPC) Systems. IEEE Journal of Lightwave Technology.
  • Karanth , A., Louri, A. (2009). Reconfigurable and Adaptive Photonic Networks for High-Performance Computing (HPC) Systems. 22. OSA Applied Optics; 44: E13-E23.
  • Karanth , A., Sarathy, A., Louri, A. (2008). Adaptive Channel Buffers in On-Chip Interconnection Networks -A Power and Performance Analysis. 9. IEEE Transactions on Computers; 57: 1169-1181.
  • Karanth , A., Louri, A. (2008). OPTISIM: A System Simulation Methodology for Optically Interconnected High-Performance Computing Systems. 5. IEEE Micro; 28: 22-36.
  • Sarathy, A., Karanth , A., Louri, A. (2008). Low-Power Low-Area Network-on-Chip Architecture using Adaptive Channel Buffers. 8. IEE Electronics Letters; 44: 512-513.
  • Karanth , A., Louri, A. (2007). A System Simulation Methodology of Optical Interconnects for High-Performance Computing(HPC) Systems. 12. OSA Journal of Optical Networking; 6: 1282-1300.
  • Kochar, C., Karanth , A., Louri, A. (2007). Proposed Low-Power High-Speed Microring Resonator-based Switching Technique for Dynamically Reconfigurable Optical Interconnects. 17. IEEE Photonics Technology Letters; 19: 1304-1306.
  • Kochar, C., Karanth , A., Louri, A. (2007). nD-RAPID: A Multi-Dimension Scalable Fault-tolerant Opto-Electronic Interconnection for Scalable High-Performance Computing Systems. 5. OSA Journal of Optical Networking, Special Issue on Photonics in Switching; 6: 465-481.
  • Karanth , A., Louri, A. (2006). RAPID for High-Performance Computing: Architecture and Performance Evaluation. 25. OSA Applied Optics, Special Issue on Information Photonics; 45: 6326-6334.
  • Karanth , A., Louri, A. (2005). Design of High-Speed Optical Interconnect for Scalable Shared Memory Multiprocessors. 1. IEEE Micro, Special Issue on Hot Interconnects; 25: 41-49.
  • Louri, A., Karanth , A. (2004). An Optical interconnection network and a modified snooping protocol for the design of Large-scale Symmetric Multiprocessors (SMPs). 12. IEEE Transactions on Parallel and Distributed Systems; 15: 1093-1104.
  • Karanth , A., Louri, A. (2004). RAPID: Reconfigurable and scalable All-Photonic Interconnect for Distributed shared memory multiprocessors. 9. IEEE/OSA Journal of Lightwave Technology, Special Issue on Optical Interconnects; 22: 2101-2110.
  • Louri, A., Karanth , A. (2003). SYMNET: An Optical Interconnection Network for Large-scale, High-Performance Symmetric Multiprocessors. 17. OSA Applied Optics; 42: 3407-3417.
  • Louri, A., Karanth , A. (2003). Parallel Optical Interconnection Network for Address Transactions in Large-scale, Cache coherent Symmetric Multiprocessors (SMPs). 2. IEEE Journal of Selected Topics in Quantum Electronics, Special Issue on Optical Interconnects; 9: 667-676.
  • Louri, A., Karanth , A. (2003). Scalable Optical Interconnection Networks for Symmetric Multiprocessors. 1. SPIE, Optics in Information Systems; 14.

Journal Article, Professional Journal (3)

  • Karanth , A., Louri, A. (2011). Introduction to the Special Issue on Network-on-Chips (NoCs). 5. Journal of Parallel and Distributed Computing; 71: 623-624.
  • Zhang, Y., Morris, R., Karanth , A. (2011). Design of a Power-Efficient Dual-Crossbar Network-on-Chip Architecture. 2. Elseiver Microprocessors and Microsystems, Embedded Hardware Design; 36: 110-118.
  • Karanth , A., Louri, A. (2011). Energy-Efficient and Bandwidth Reconfigurable Photonic Networks for High-Performance Computing (HPC) Systems. 2. IEEE Journal of Selected Topics in Quantum Electronics; 17: 384-395.

Patent (6)

  • Karanth , A., Louri, A., Sarathy, A., Wang, J. Fault-and Variation-Tolerant Energy-and Area-Efficient Links for Network-on-Chips (NoCs). OU08019.
  • Karanth , A., Louri, A., Sarathy, A., Wang, J. iDEAL:Inter-Router Dual-function Energy and Area-Efficient Links for Network-on-Chips(NoCs). UA08-078.
  • Shiflett, K., Karanth , A. Optical Multiply and Accumulate Unit. 20210264241.
  • Karanth , A., Shiflett, K. Optical Multiply-Accumulate (OMAC) Unit.
  • Kaya, S., Karanth , A., Canan, T. Ambipolar Field-Effect Device using Engineered Work-Function”. 16/445,824.
  • Karanth , A., DiTomaso, D., Louri, A. Directional allocation of communication links based on data traffic loads . 10,148,593.

Book, Chapter in Scholarly Book (2)

  • Karanth , A., Louri, A., Morris, R. (2016). Scalable 3D Optical Interconnects for Data centers. Woodhead Publishing.
  • Karanth , A., Louri, A. (2004). Optical Interconnection Network for High-Performance Parallel Computers. Trivandrum: Research Signpost, Recent Research Development in Optics; 4.

Conference Proceeding (95)

  • Cunningham, G., Chenji, H., Juedes, D., Karanth , A. (2024). d-GUARD: Thwarting Denial-of-Service Attacks via Hardware Monitoring of Information Flow using Language Semantics in Embedded Systems. Incheon, South Korea: 29th Asia and South Pacific Design Automation Conference (ASP-DAC 2024).
  • Li, Y., Louri, A., Karanth , A. (2023). A Silicon Photonic Multi-DNN Accelerator. Vienna, Austria: 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT-23).
  • Shiflett, K., Karanth , A., Louri, A., Bunescu, R. (2023). Flumen: Dynamic Processing in the Photonic Interconnect. Orlando, Florida: 50th IEEE International Symposium on Computer Architecture (ISCA); 14.
  • Cunningham, G., Juedes, D., Stewart, G., Chenji, H., Karanth , A. (2023). DAGGER: Exploiting Language Semantics for Program Security in Embedded Systems. San Fransisco, CA: 24th International Symposium on Quality Electronic Design (ISQED).
  • Wolff, A., Shiflett, K., Karanth , A. (2023). Photonic Interconnect Based Neural Network Simulator. IEEE Silicon Photonics Conference.
  • Mourning, C., Chenji, H., Hallman-Thrasher, A., Kaya, S., Abukamail, N., Juedes, D., Karanth , A. (2023). Reflections of Cybersecurity Workshop for K-12 Teachers. ACM SIGCSE.
  • Yuhaz, N., Me'Kayla, T., Shiflett, K., Miller, E., Ranganathan, P., Karanth , A., Choe, H. (2022). Advanced Machine Learning Techniques to Predict GvhD Occurrence and Severity with High Accuracy. New Orleans, Louisiana: 64th ASH Annual Meeting and Exposition.
  • Mourning, C., Juedes, D., Hallman-Thrasher, A., Chenji, H., Kaya, S., Karanth , A. (2022). Reflections of Cybersecurity Workshop for K-12 Teachers and High School Students. New York, NY, USA: Association for Computing Machinery; 1127. https://doi.org/10.1145/3478432.3499094.
  • Li, Y., Louri, A., Karanth , A. (2022). SPACX: Silicon Photonics-based Chiplet Architecture for DNN Inference. Seoul, South Korea: 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA).
  • Liu, S., Karanth , A. (2021). Dynamic Voltage and Frequency Scaling to Improve Energy-Efficiency of Hardware Accelerators. 28th IEEE International Conference on High-Performance Computing, Data & Analytics (HiPC).
  • Li, Y., Louri, A., Karanth , A. (2021). Scaling Deep Learning Inference with Chiplet-based Architecture and Photonic Interconnects. 58th Design Automation Conference (DAC).
  • Wolff, A., Shiflett, K., Karanth , A. (2021). Parallel Dot Product using Silicon Photonics. IEEE Photonics Conference (IPC).
  • Liu, S., Karmunchi, S., Laha, S., Kaya, S., Karanth , A. (2021). WiNN: Wireless Interconnect based Neural Network Accelerator. 39th International Conference on Computer Design (ICCD).
  • Shiflett, K., Karanth , A., Louri, A., Bunescu, R. (2021). Bitwise Neural Network Acceleration using Silicon Photonics. 31st ACM Great Lakes Symposium on VLSI.
  • Shiflett, K., Karanth , A., Louri, A., Bunescu, R. (2021). Albireo: Energy-Efficient Acceleration of Convolutional Neural Networks via Silicon Photonics. 48th International Symposium on Computer Architecture (ISCA).
  • Li, J., Louri, A., Karanth , A., Bunescu, R. (2021). CSCNN: Algorithm-Hardware Co-Design for CNN Accelerators using Centrosymmetric Filters. 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA-21).
  • Li, J., Louri, A., Karanth , A., Bunescu, R. (2021). GCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional Neural Network. 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA-21).
  • Canan, T., Kaya, S., Karanth , A., Louri, . (2020). 4-Input NAND and NOR Gates Based on Two Ambipolar Schottky Barrier FinFETs. Glasgow, Scotland, UK: 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS).
  • Shiflett, K., Karanth , A., Louri, A., Bunescu, R. (2020). Energy-Efficient Multiply-and-Accumulate Using Silicon Photonics for Deep Neural Networks. Vancouver, British Columbia: IEEE Photonics Conference (IPC).
  • Canan, T., Kaya, S., Chenji, H., Karanth , A. (2020). Reconfigurable Gates with Sub-10nm Ambipolar SB-FinFETs for Logic Locking & Obfuscation. IEEE; http://dx.doi.org/10.1109/mwscas48704.2020.9184509.
  • Clark, M., Chen, Y., Karanth , A., Ma, B., Louri, A. (2020). DoZZNoC: Reducing Static and Dynamic Energy in NoCs with Low-Latency Voltage Regulators using Machine Learning. New Orleans, LA: 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2020).
  • Shiflett, K., Wright, D., Karanth , A., Louri, A. (2020). PIXEL: Photonic Neural Network Accelerator . San Diego, CA: 26th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2020).
  • Wang, K., Louri, A., Karanth , A., Bunescu, R. (2019). IntelliNoC: A Holistic Framework for Energy-Efficient and Reliable On-chip Communication for Manycores. 46th International Symposium on Computer Architecture (ISCA); https://dl.acm.org/doi/10.1145/3307650.3322274.
  • Wang, K., Louri, A., Karanth , A., Bunescu, R. (2019). High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design using Reinforcement Learning. 22nd Design, Automation and Test in Europe (DATE) conference; https://ieeexplore.ieee.org/document/8714869.
  • Canan, T., Kaya, S., Karanth , A., Louri, A., Xin, H. (2018). 10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETs. 2018 IEEE International Conference on Electronics, Circuits & Systems (ICECS).
  • Boraten, T., Karanth , A. (2018). Securing NoCs Against Timing Attacks with Non-Interference Based Adaptive Routing. 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS); 1-8.
  • Canan, T., Kaya, S., Karanth , A., Louri, A., Xin, H. (2018). Sub-THz Tunable Push Push Oscillators with FinFETs for Wireless NoCs. 61st IEEE International Midwest Symposium on Circuits & Systems (MWSCAS).
  • Clark, M., Karanth , A., Bunescu, R., Louriu, A. (2018). LEAD: Learning-enabled Energy-Aware Dynamic Voltage/Frequency Scaling in NoCs. San Francisco: The 55th Annual Design Automation Conference (DAC); http://ace.cs.ohio.edu/~razvan/papers/dac18.pdf.
  • Karanth , A., Shifflet, K., Kaya, S., Laha, S., Louri, A. (2018). Scalable Power-Efficient Kilo-Core Photonic-Wireless NoC Architectures. 2018 IEEE International Parallel and Distributed Processing Symposium (IPDPS); 1010-1019.
  • Van Winkle, S., Karanth , A., Bunescu, R., Louri, A. (2018). Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning. Vienna: The 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA); http://ace.cs.ohio.edu/~razvan/papers/hpca18.pdf.
  • Sharma, Y., Wu, J., Kantemur, A., Tak, J., Karanth , A., Kaya, S., Louri, A., Xin, H. (2018). Reconfigurable Intra-Chip Antenna for Future Wireless Communications. Proceedings of 2018 USNC-URSI.
  • Canan, T., Kaya, S., Karanth , A., Louri, A., Xin, H. (2017). Ultra-Compact Sub-10nm Logic Circuits based on Ambipolar SB-FinFETs. Boston, MA: 60th IEEE International Midwest Symposium on Circuits & Systems (MWSCAS).
  • Canan, T., Kaya, S., Karanth , A., Xin, H., Louri, A. (2017). Ultra-Compact sub-10nm Logic Circuits Based on Ambipolar SB-FinFETs. IEEE; 100-103. http://www.mwscas2017.org.
  • Kelestemur, Y., Laha, S., Kaya, S., Karanth , A., Xin, H., Louri, A. (2017). mm-Wave tunable colpitts oscillators based on FinFETs. IEEE; 1--6. http://www.wamicon.org/2017/.
  • DiTomaso, D., Sikder, A., Karanth , A., Louri, A. (2017). Machine Learning Enabled Power-Aware Network-on-Chip Design. Lausanne: Design and Test in Europe (DATE'17).
  • DiTomaso, D., Boraten, T., Karanth , A., Louri, A. (2016). Dynamic error mitigation in NoCs using intelligent prediction techniques. 1–12.
  • Alshraiedeh, J., Karanth , A. (2016). An adaptive routing algorithm to improve lifetime reliability in NoCs architecture. 127–130.
  • Sikder, A., Karanth , A., Louri, A. (2016). Reconfigurable Optical and Wireless (R-OWN) Network-on-Chip for High Performance Computing. 25.
  • Sikder, M., Karanth , A., Rayess, W., DiTomaso, D., Matolak, D., Kaya, S. (2016). Exploring Wireless Technology for Off-Chip Memory Access. 92–99.
  • Van Winkle, S., Ditomaso, D., Kennedy, M., Karanth , A. (2016). Energy-efficient optical Network-on-Chip architecture for heterogeneous multicores. 62–63.
  • Boraten, T., Karanth , A. (2016). Mitigation of Denial of Service Attack with Hardware Trojans in NoC Architectures. 1091–1100.
  • Kennedy, M., Karanth , A. (2016). On-demand laser power allocation for on-chip optical interconnects. 68–69.
  • Boraten, T., DiTomaso, D., Karanth , A. (2016). Secure Model Checkers for Network-on-Chip (NoC) Architectures. 45–50.
  • Boraten, T., Karanth , A. (2016). Packet security with path sensitization for NoCs. 1136–1139.
  • Kennedy, M., Karanth , A. (2015). Cross-Chip: Low Power Processor-to-Memory Nanophotonic Interconnect Architecture. Las Vegas, NV: Workshop on Energy-Efficient Networks of Computers (E2NC): from the Chip to the Cloud in Conjuction with (IGSC'15).
  • Karanth , A., Neel, B., Brantley, W. (2015). Power and Performance Analysis of Scalable Photonic Networks for Exascale Architecture. Las Vegas, NV: 6th IEEE International Green and Sustainable Computing Conference (IGSC'15).
  • Karanth , A., Sikder, A., DiTomaso, D., Kaya, S., Laha, S., Matolak, D., Rayess, W. (2015). Kilo-core Wireless Network-on-Chips (NoCs) Architectures. Article 33. New York, NY: ACM; 6 pages. http://dl.acm.org/citation.cfm?id=2800797.
  • Sikder, A., Karanth , A., Kennedy, M., Kaya, S., Lori, A. (2015). OWN: Optical and Wireless Network-on-Chips (NoCs) for Kilo-core Architectures. 44-51. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7312666&isnumber=7312546.
  • Neel, B., Kennedy, M., Karanth , A. (2015). Runtime Power Reduction Techniques in On-Chip Photonic Interconnects. Pittsburgh, Pennsylvania: 25th ACM's Great Lakes VLSI Symposium (GLSVLSI'15).
  • Kennedy, M., Karanth , A. (2015). Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-Clockwise Optical Routing. Bangalore, India: 28th International Conference on VLSI Design.
  • Laha, S., Kaya, S., Karanth , A., Matolak, D. (2014). LC Oscillators in Nanoscale DG-MOSFETs. Tampa, Florida: IEEE 15th Wireless and Microwave Technology Conference (WAMICON); 1-5. http://dx.doi.org/10.1109/WAMICON.2014.6857767.
  • DiTomaso, D., Karanth , A., Louri, A. (2014). QORE: A Fault-Tolerant Network-on-Chip Architecture with Power-Efficient Quad Function Channel (QFC) Buffer. Orlando, FL: 20th IEEE International Symposium on High-Performance Computer Architecture (HPCA).
  • Laha, S., Kaya, S., Karanth , A., Matolak, D. (2013). W-band Power Amplifier in 0.15μm InGaAs pHEMT Technology with Microstrip Transmission Lines. Bethesda, MD: 7th International Semiconductor Device Research Symposium – ISDRS.
  • Boraten, T., Karanth , A. (2013). Energy-efficient Runtime Adaptive Scrubbing in fault-tolerant Network-on-Chips (NoCs) architectures. Ashville, NC: 31st IEEE International Conference on Computer Design (ICCD); 264 - 271.
  • Kaya, S., Laha, S., DiTomaso, D., Karanth , A., Matolak, D., Rayess, W. (2013). On Ultra-Short Wireless Interconnects for NoCs and SoCs: Bridging the 'THz' Gap. Columbus, Ohio: 56th IEEE International Midwest Symposium on Circuits & Systems (MWSCAS).
  • Morris, R., Karanth , A., Louri, A. (2013). Evaluating the Scalability and Performance of 3D Stacked Reconfigurable Nanophotonic Interconnects. Austin, TX: 15th IEEE/ACM System Level Interconnect Prediction (SLIP) colocated with Design Automation Conference (DAC).
  • DiTomaso, D., Morris, R., Jolley, E., Sarathy, A., Louri, A., Karanth , A. (2013). Energy-Efficient, Fault-Tolerant Unified Buffer and Bufferless Crossbar Architecture for NoCs. Boston, Massachusetts: Workshop on High-Performance Power-Aware Computing (HPPAC), held in conjuction with IPDPS'13.
  • DiTomaso, D., Karanth , A., Matolak, D., Kaya, S., Laha, S., Rayess, W. (2013). Energy-Efficient Adaptive Wireless NoCs Architecture. Tempe, Arizona: IEEE/ACM 7th International Symposium on Networks-on-Chip (NoCs); 1-8.
  • Zhou, L., Karanth , A. (2013). PROBE: Prediction-based Optical Bandwidth Scaling for Energy-Efficient NoCs. Tempe, Arizona: IEEE/ACM 7th International Symposium on Networks-on-Chip (NoCs); 1-8.
  • Laha, S., Kaya, S., Karanth , A., Matolak, D. (2013). 60 GHz Tunable LNA in 32 nm Double Gate MOSFET for a Wireless NoC Architecture. Orlando, Florida: 14th Annual IEEE Wireless and Microwave Technology Conference (WAMICON’13); 1-4.
  • Morris, R., Karanth , A., Louri, A. (2012). Reconfiguration of 3D Photonic Network-on-Chips for Maximizing Performance and Improving Fault Tolerance. Vancouver, Canada: 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-45).
  • Laha, S., Kaya, S., Karanth , A., Matolak, D. (2012). 60 GHz OOK Transmitter in 32 nm DG FinFET. Maui, Hawaii: IEEE International Conference on Wireless Information Technology and Systems.
  • Morris, R., Karanth , A., Louri, A. (2012). 3D-NoC: 3D Reconfigurable Nanophotonic Interconnects for Multicores. Montreal, Canada: 30th IEEE International Conference on Computer Design (ICCD).
  • DiTomaso, D., Laha, S., Karanth , A., Kaya, S., Matolak, D. (2012). Evaluation and Performance Analysis of Energy Efficient Wireless NoC Architecture. Boise, Idaho: 55th International Midwest Symposium on Circuits & Systems (MWSCAS).
  • DiTomaso, D., Boraten, T., Karanth , A., Louri, A. (2012). Evaluation of Fault Tolerant Channel Buffers for Improving Reliability in NoCs. Boise, Idaho: 55th International Midwest Symposium on Circuits & Systems (MWSCAS).
  • DiTomaso, D., Laha, S., Karanth , A., Kaya, S., Matolak, D. (2012). Energy-Efficient Modulation for a Wireless Network-on-Chip Architecture. Montreal, Canada: 10th IEEE International NEWCAS Conference.
  • Neel, B., Morris, R., DiTomaso, D., Karanth , A. (2012). Power-Efficient Photonic Network for Many-core Architectures. San Jose, California: Workshop on Lighter-than-Green Dependable Multicore Architectures, held in conjunction with IEEE International Green Computing Conference (IGCC-3).
  • Zhang, Y., Morris, R., DiTomaso, D., Karanth , A. (2012). Energy-Efficient, Fault-Tolerant Unified Buffer ad Bufferless Crossbar Architecture for NoCs. Shanghai, China: Workshop on High-Performance Power-Aware Computing (HPPAC), held in conjunction with IPDPS’12.
  • Laha, S., Kaya, S., Karanth , A., Matolak, D. (2012). Double Gate MOSFET Based Efficient Wide Band Tunable Power Amplifiers. Cocoa Beach, Florida: 13th Annual IEEE Wireless and Microwave Technology Conference.
  • Karanth , A., Morris, R., DiTomaso, D., Sarathy, A., Louri, A. (2011). Co-Design of Channel Buffers and Crossbar Organizations in NoCs Architecture. IEEE/ACM International Conference on Computer-Aided Design (ICCAD’11).
  • DiTomaso, D., Karanth , A., Kaya, S., Matolak, D. (2011). iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture. New Jersey: IEEE 19th Symposium on High-Performance Interconnects (Hot Interconnects); 8. http://dx.doi.org/10.1109/HOTI.2011.12.
  • Morris, R., Karanth , A. (2011). Design of a High-Speed Nanophotonic Architecture for Cache Coherent Multicores. Los Angeles, CA: Optical Fiber Communication Conference & Exposition (OFC’11); OThQ6.
  • Morris, R., Karanth , A. (2010). Scalable Nanophotonic Interconnect for Cache Coherent Multicores. Workshop on the Interaction between Nanophotonic Devices and Systems (WINDS).
  • Morris, R., Karanth , A. (2010). Design of On-Chip Networks using Mircoring Resonator Based Nanophotonic Crossbar for Future Multicores. IEEE Photonics Annual Meeting.
  • Morris, R., Karanth , A. (2010). Power-Efficient and High-Performance Multi-Level Hybrid Nanophotonic Interconnect for Multicores. IEEE/ACM Symposium on Network-on-Chips (NoCs’10); 207-214.
  • Sun, J., Lysecky, R., Shankar, K., Karanth , A., Louri, A., Wang, J. (2010). Workload Capacity Considering NBTI Degradation in Multi-core Systems. Proceedings of the IEEE 15th Asia and South Pacific Design Automation Conference (ASP-DAC'10); 450-455.
  • Karanth , A., Morris Jr, R., Louri, A., Zhang, X. (2009). On-Chip Photonic Interconnects for Scalable Multi-core Architectures. San Diego, California: 3rd ACM/IEEE International Symposium on Network-on-Chip.
  • Karanth , A., Louri, A., Wang, J. (2009). Energy-Efficient Router Buffers with Bypassing for Network-on-Chips (NoCs). San Jose, California: 10th International Symposium on Quality Electronic Design (ISQED’09); 826.
  • Jin, S., Karanth , A., Louri, A., Wang, J. (2009). NBTI Aware Workload Bal¬ancing in Multicore Systems. San Jose, California: 10th International Symposium on Quality Electronic Design (ISQED’09); 833.
  • Karanth , A., Sarathy, A., Louri, A. (2009). Adaptive Inter-Router Links for Low-Power, Area-Efficient and Reliable Network-on-Chip (NoC) Architecture. Yokohama: 14th Asia and South Pacific Design Automation Conference (ASP-DAC).
  • Karanth , A., Louri, A. (2008). Efficient Dynamic Bandwidth Re-allocation in Photonic Networks using SOI-based Microring Resonators. Rochester, NY: Frontiers in Optics, OSA Annual Meeting, FTuA2.
  • Karanth , A., Sarathy, A., Louri, A. (2008). iDEAL:Inter-router Dual-function Energy- and Area-Efficient Linkdesign for Network-on-Chip (NoC) Architecture. Beijing: 35th International Symposium on Computer Architecture (ISCA-35); 241-250.
  • Karanth , A., Sarathy, A., Louri, A. (2007). Design of Energy-Efficient Adaptive Channel Buffers for Network-on-Chips Architecture. Orlando, Florida: Proceedings of ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS’07).
  • Karanth , A., Louri, A. (2007). Performance Adaptive Power-Aware Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems. Reno, Nevada: Proceedings of the International Conference for High-Performance Computing, Networking, Storage and Analysis (SC’07).
  • Kochar, C., Karanth , A., Louri, A. (2007). Implementation of DynamicBandwidth Re-allocation in Optical Interconnects using Microring Resonator. Stanford, California: Proceedings of 15th Annual IEEE Symposiumon High-Performance Interconnects (HotInterconnects ’07); 54-64.
  • Karanth , A., Louri, A. (2007). Power-Aware Bandwidth Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems. Long Beach, California: 21st IEEE International Parallel and Distributed Processing Symposium,(IPDPS’07).
  • Karanth , A., Louri, A. (2006). A New Technique for Dynamic Bandwidth Reallocation in Optically Interconnected High-Performance Computing Systems. Stanford University, California: 14th Annual IEEE Symposium on High-Performance Interconnects (Hot Interconnects 14).
  • Karanth , A., Louri, A. (2005). Switchless Photonic Architecture for Parallel Computers. Tucson, Arizona: Frontiers in Optics, 89th OSA Annual Meeting.
  • Karanth , A., Louri, A. (2005). Scalable Optical Interconnection Network for Parallel and Distributed Computing. Charlotte, North Carolina: Information Photonics, Optical Society of America.
  • Karanth , A., Louri, A. (2004). Design of a High-Speed Optical Interconnect for Scalable Shared Memory Multiprocessors. Stanford University, California: 12th Annual IEEE Symposium on High Performance Interconnects (Hot Interconnects).
  • Karanth , A., Louri, A. (2004). A Scalable Architecture for Distributed Shared Memory Multiprocessors using Optical Interconnects. Santa Fe, New Mexico: 18th International Parallel and Distributed Processing Symposium (IPDPS’04).
  • Louri, A., Karanth , A. (2003). Parallel Optical Interconnection Network for SMPs. Tucson, Arizona: Frontiers in Optics, 87th OSA Annual Meeting.
  • Louri, A., Karanth , A. (2003). Design of Large-scale Symmetric Multiprocessors (SMPs) using Parallel Optical Interconnects. Tunis: ACS/IEEE International Conference on Computer Systems and Applications, AICCSA ’03.
  • Karanth , A., Louri, A. (2002). Optical Interconnects for Large-Scale Symmetric Multiprocessor Networks. Tapei: In Proc. OSA/IEEE , Optics in Computing 2002.
  • Karanth , A., Louri, A. (2001). Y-junction Based addressing in Optical Symmetric Multiprocessor Neworks. La Jolla, San Diego: Proc. International Annual Meeting of the Lasers and Electro-Optics Society, LEOS 2001; 68-72.